1. Field of the Invention
This invention pertains to electronic memories and in particular to nonvolatile memory cells and cell organization suitable for operation with byte alterability of the nonvolatile information stored in the memory.
2. Prior Art
There is a long history of nonvolatile memory devices and more particularly electrically erasable programmable read only memory (EEPROM) devices. All prior art commercial byte alterable EEPROMs have used N channel devices as the memory transistor. Such an N channel EEPROM cell 10 typical of current technology is shown in the top view of FIG. 1a and the cross section of FIG. 1b. 
As shown in FIG. 1a there are two layers of polycrystalline silicon 13 and 14 formed on and insulated from silicon substrate 24. The cell includes select transistor 29 and memory transistor 28. The substrate under memory transistor 28 is doped P type except where locally doped N type to form source/drain regions 16 and 23. The first layer of polycrystalline deposited is called poly 1. The poly 1 feature 14 has no connections to other conductors and is therefore referred to as a floating gate. This portion of the poly 1 layer forms the gate of memory transistor 28. The second layer of polycrystalline silicon, called poly 2, is used to form a transistor 29, having polycrystalline silicon gate 12, that acts as a select transistor between contact 19 and memory transistor 28. Poly 2 layer is also used to form control gate 13 of memory transistor 28, which is capacitively coupled to floating gate 14.
N type region 15 is located under a thin tunnel oxide window 11. Region 15 is used during programming and erasing. (In this application, the IEEE standard 1005 will be followed consistently for nomenclature. Therefore, programming is defined as putting electrons onto the floating gate and erasing is defined as removing electrons from the floating gate.) There is also a buried diffusion 17 on the source side of the memory transistor 28. This is included merely so that the channel length is not alignment sensitive and could be omitted without loss of functionality. The buried diffusions are so called because they lie under the polycrystalline silicon layers. (In some designs they also lie under the field oxide.) Thick field oxide 18, which exists outside of the xe2x80x9cTxe2x80x9d shaped region of thin oxide bounded by the heavy lines in FIG. 1a, provides isolation between the transistors and the N type diffusions where desired. The regions under field oxide 15 may have enhanced P type doping relative to the regions under the gates in order to raise the threshold voltages of the parasitic field transistors.
Typical operation will have floating gate 14 charged positively with respect to ground when erased and charged negatively with respect to ground when programmed. To read memory transistor 28, control gate 13 is grounded and gate 12 of select transistor 29 is biased positively to provide a low resistance path from its drain contact 19 to drain 15 of memory transistor 28. Drain contact 19 provides connection to metal bit line 25 as is seen in the cross section view of FIG. 1b (the metal is omitted from the top view of FIG. 1a in the interests of clarity). Bit line 25 is biased at a modest positive voltage (e.g. 2 V) and the common source line 16 is biased at ground. If floating gate 14 is erased, current can flow from bit line 25 to source region 16. If floating gate 14 is programmed, memory transistor 28 is in a nonconducting state and no current flows. The presence or absence of current flow is sensed to determine the state stored by memory transistor 14.
The oxide in tunnel window 11 is typically about 10 nm thick. To program memory cell 28, floating gate 14 must be capacitively coupled to a sufficiently positive potential with respect to drain 15 that a field of about 10 MV/cm appears across tunnel oxide 11. This is accomplished by biasing poly 2 control gate 13 at about 20 V while biasing select gate 12 at a sufficiently high potential that select transistor 29 is conducting with bit line 25 at ground potential. Under these conditions, drain region 15 provides a source of electrons on the cathode side of tunnel oxide 11. With 10 MV/cm appearing across tunnel oxide 11, Fowler-Nordheim tunneling occurs and charges floating gate 14 negatively.
To erase memory transistor 28, the bias across tunnel oxide 11 must be reversed. This is accomplished by applying a high bias to drain 15 of memory transistor 28 while poly 2 control gate 13 is biased at ground in order to keep control gate 13 capacitively coupled to a low voltage. The high voltage is applied to drain 15 of memory transistor 28 by applying the desired voltage to bit line 25 while gate 12 of select transistor 29 is biased at a potential that is higher than the desired voltage by at least the threshold voltage of select transistor 29.
The operation of this cell in an array can be understood with reference to FIGS. 2a and 2b, which shows a portion of a prior art memory array 38 including a single word line 31 and associated bit lines 32-0 through 32-7, thereby forming a portion of a memory capable of storing a single 8 bit word. (In this and subsequent schematic drawings, the transistor gate with a small notch directed at the channel region is used indicate a transistor in which one portion of the gate oxide has been thinned to enhance the tunneling current.) To write a desired data pattern into a word, all bits of the word are first programmed and then selected bits are erased to achieve the desired pattern. Selection of the word to be programmed is achieved with the combination of word line 31 and word line select transistor 37 in FIG. 2b. A high voltage, VPP+VTN, where VPP is a positive programming voltage (typically approximately 18 volts) and VTN is the threshold voltage of an N channel transistor (typically approximately 4 volts with 18 V of source bias), is applied to word line 31 to select the desired row of the memory array. VPP is applied to column 35 associated with the desired word. This voltage passes through word select transistor 37 to the control gates 34-0 through 34-7 of all of the transistors in the word to be programmed. During this program operation all bit lines are biased at VSS. After all of the floating gates in the selected word are programmed, VSS (ground) is applied to line 35 and VPP is applied to those bit lines 32-0 through 32-7 containing bits that are to be erased, while the bit lines containing bits that are not to be erased remain biased at VSS.
There is a convenient consequence of this particular sequence of writing operations. Because all transistors in the selected word are initially programmed, they are in a nonconducting state when their control gates are grounded by applying VSS to line 35. When VPP is applied to the selected bit lines, the floating gates of the selected transistors are erased into a conducting state and the common source line 35 is charged up. However, the voltage on the common source line is limited to Vfgxe2x88x92VTN, where Vfg is the floating gate potential and VTN is the threshold of the memory transistor when neutralized by extended exposure to ultraviolet light. This moderate voltage is too small to punch through the programmed transistors and so no current flows from the bit lines that are biased at VPP to those that are biased at VSS. It is this lack of direct current path that makes it possible to operate commercial EEPROMs from a single logic level power supply with all of the needed high voltages being generated on the chip by relatively small, low power charge pumps.
There are a couple of features of this prior art that limit its desirability for application in integrated circuit products in which only a small number of EEPROM bits are desired in a circuit that is primarily logic or a mixed signal product. The prior art cell depicted in FIGS. 1a and 1b has at least three additional masking steps that are not required for the fabrication of an MOS structure containing logic circuitry but not containing EEPROM cells: the second layer of polycrystalline silicon, the thin tunnel oxide window, and the buried N region under the polycrystalline silicon floating gate. These masking steps and the processes associated with them add cost to the manufacturing process, perhaps as much as 20% to the cost of manufacturing a CMOS wafer. This is a high price to pay for functionality that is only used in a small portion of the product when only a small number of EEPROM bits are required. To reduce this cost, there have been a number of single poly EEPROM cells developed. This reduces somewhat the cost of adding EEPROM functionality to a circuit, but is still more expensive than is really desirable because of the continuing need for the additional processing steps associated with forming the tunnel oxide window and the diffusions 15 and 17.
A second hindrance to incorporating EEPROM technology into existing CMOS processes is the relatively high voltages required for the write operation. An electric field of about 10 MV/cm across the tunnel oxide is required for a sufficiently large Fowler-Nordheim tunneling current to write to a cell in times measured in msec. In addition, not all of the voltage applied to the control gate is coupled to the floating gate. In practical cases, the capacitive coupling ratio between the control gate and the floating gate is in the range 0.6 to 0.8 (i.e. 60 to 80% of voltage applied to the control gate is coupled to the floating gate). This means that VPP greater than about 12 V is required between the control gate and the tunneling diffusion in the substrate. To achieve this a voltage which was earlier expressed as (VPP+VTN) must be applied to the row line. The VTN in this equation is not the usual threshold voltage measured with the body of the N channel transistor grounded; rather this voltage threshold is the voltage threshold with the body of the transistor at xe2x88x92VPP as a result of the voltage on its source. When VPPis approximately 12 V, the threshold voltage can easily be increased as a result of the body effect to about 3 V. This results in a voltage of at least about 15 V being applied to the word line. Many logic processes will not reliably support a voltage of this magnitude.
In accordance with the teachings of this invention, these limitations are alleviated by reducing the magnitude of the applied voltage required for writing and by simplifying the fabrication process, thereby reducing manufacturing costs. To accomplish these ends, P channel EEPROM cells have been developed. These cells are designed for integration into arrays that can be written with single polarity signals that can be developed from relatively small, low power charge pumps that can be integrated into the integrated circuit products. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step in some embodiments. Furthermore, the novel cells of this invention enable the array to function with a value of VPP that is about 2 V less than that required by an N channel EEPROM cell of the prior art, with similar writing speed and tunnel oxide thickness.
Among the advantages of this invention are that it has the potential for significantly decreasing the development time and cost because it makes less stringent demands on the high voltage capability of the process and that it can decrease the cost for processing a wafer by 3 to 5%.
The focus of this invention is developing P channel EEPROM cells that can be integrated into arrays and supported with on chip circuitry so that the array is suitable for inclusion into an integrated circuit that is to function from a single voltage power supply. For use in practical array it is necessary to have cells that can be set into states to represent an arbitrary pattern of ones and zeroes. In the conventional N channel EEPROM, this is accomplished by programming all of the bits within a word and then erasing selected bits to establish a defined pattern within the array. There are select transistors so that words that are not intended to be written are isolated from the high voltages used for programming and erasure.
This invention includes three methods for performing these functions in a P channel array. In a first method, the cells within a word are all programmed, i.e. electrons are injected onto the floating gates, and then selectively erased. Because a P channel MOSFET with a gate negatively charged is in the conducting mode, a transistor is provided between the floating gate and the source in all of the cells in order to allow isolation of the cells form the common source during the selective erase. If the cells are connected through a common source during the erase, current will flow from the drain of the cell or cells that are to be erased to the drain(s) of those cell(s) that are not to be erased. Such a current would load any practicable on chip charge pumps such that the voltage applied to the drains to be erased would be limited to a low enough value that erasure would not occur. Adding a source select transistor allows current flow through the floating gate transistor to the source to be inhibited during the erase mode, but enabled during the read mode to provide a sense current.
A second method of operation described in this invention functions by erasing all bits within a word and then selectively programming those that are to be in the programmed state. With this method all the cells in a word can share a common source line. The selective programming is accomplished by providing a select transistor to the capacitor that controls the potential on the floating gate. This select transistor provides for matrix addressing of the control capacitor on a bit by bit basis.
In an alternative embodiment, a tunneling window under the floating gate is not used, but rather the entire gate area of the memory transistor lies over a thin tunnel oxide region. This allows a shorter channel length, a simpler fabrication process, and therefore a lower cost device. This approach has the further advantage that the memory transistor provides more read current for a given floating gate potential.
In another embodiment of this invention, individual source select transistors in each cell are not required. In this embodiment, a separate source line is run through the array for each column so that a shared source select transistor is used to provide the necessary isolation for all of the memory transistors on a column. In this manner, a substantial decrease in array area is achieved. In another embodiment, the source and drain select transistors are omitted. The cell is programmed by biasing the control gate to a high voltage with the N well at ground and other nodes either floating or at ground. The selected cells are erased by biasing the bit lines of the selected cells at VPP while the biases applied to the other cells in the array are such that the voltage across the gate oxide is maintain at a low enough voltage that significant tunneling does not occur.